The manufacturers of state of the art audio and video systems are increasingly demanding multiple-format integrated circuits which include a combination of analog to digital converters (ADCs), digital to analog converters (DACs), and/or pulse width modulation (PWM) controllers fabricated together on a single chip. The design of such multiple-format integrated circuits presents a number of significant challenges to the chip design, particularly in regards to the management of on-chip noise.
Most audio and video system applications require compatible data ports for exchanging digital data between devices and subsystems. For example, a typical audio serial data port includes a serial data (SDATA) pin for inputting a serial audio data (SDATA) bitstream, in the case of a DAC or PWM controller, or for outputting an SDATA, bitstream, in the case of an ADC. Typically, each bit of the SDATA bitstream is clocked in or out of the SDATA pin in response to an associated serial clock (SCLK) signal. A sampling clock, having a frequency corresponding to the digital sample rate, partitions the SDATA bit stream into samples of one or more serial bits each. In the specific example of a stereo audio system, the sampling clock is a left-right clock (LRCK) signal, which time-multiplexes samples of left- and right-channel audio data into the SDATA bitstream.
A typical audio serial data port operates in either a master mode or a slave mode. In the master mode, the SCLK and LRCK clock signals are generated internally, in response to a received master clock (MCLK) signal, and output to the destination of the SDATA bitstream, in the case of an ADC. In the slave mode, the SCLK and LRCK clock signals are received from the source or destination of the SDATA bitstream. The MCLK signal in the slave mode is either received from external circuitry synchronized with the LRCK signal or recovered by an on-chip phase-locked loop (PLL) from the LRCK signal.
Advantageously, the utilization of serial ports minimizes the number of pins and associated on-chip driver circuitry. Given the increasing demand for multiple-format integrated circuits, as well as the overall goal of achieving high on-chip noise performance, new noise management techniques are required for utilization in integrated circuits including one or more data ports that can operate in an asynchronous mode.